1. Field of the Invention
The present invention relates to an output buffer which provides a signal from a first circuit to a second circuit which operates with signals at a higher voltage level than the first circuit.
2. Description of the Related Art
With microprocessors manufactured using process technology enabling transistor size to be reduced well below submicron level, the maximum source to drain, gate to drain and gate to source voltage which such transistors can tolerate is likewise reduced. For instance, with one process referred to here as a 2.5 volt circuit process, transistor gate oxide thickness is reduced so that the maximum gate to source, gate to drain, or drain to source voltage a microprocessor transistor can tolerate without failure is approximately 2.7 volts.
The reduced size of the transistors utilized in microprocessors enables an increase in operation speed as well as an increase in density of transistors which can be integrated onto a single chip. Because of the increase in speed and density of transistors, the process technology utilized in manufacturing microprocessors is also desirable for use in other circuits.
For example programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), are some times utilized to perform the function similar to a microprocessors. The desirable operation speed and transistor density for PLDs is similar to microprocessors, so it would be desirable to use the same processing technology to manufacture such PLDs. However, unlike microprocessors, PLDs are utilized as is glue logic to connect to devices with an operation voltage range which transistors made using the 2.5 volt circuit process will not tolerate.
For instance, PLDs typically connect to CMOS logic devices which operate over a 0-5 volt range, as well as TTL devices which operate over a 0-3.3 volt range. Although a transistor made using the 2.5 volt circuit process can produce a TTL output high of 2.4 volts, it is desirable for such a device to produce a voltage significantly higher than the 2.4 volt legal output high to assure errors do not occur.
The present invention provides an output buffer including transistors which tolerate a maximum gate to source, gate to drain, or drain to source voltage (hereinafter xe2x80x9cthe maximum tolerable voltagexe2x80x9d), such as 2.7 volts for the 2.5 volt circuit process, the transistors being configured to produce a voltage significantly higher than the maximum tolerable voltage at the buffer output.
The present invention is an output buffer including a pull up transistors having source to drain paths connected in series to connect a voltage reference higher than the maximum tolerable voltage to an output of the buffer. The buffer further includes pull down transistors having source to drain paths connected in series to connect the buffer output to ground. The buffer further includes power supply circuitry to apply gate voltages to the pull up and pull down transistors so that the voltage potential from the source to drain of each of the pull up transistors and pull down transistors is less than the maximum tolerable voltage, even when the voltage at the buffer output is greater than the maximum tolerable voltage.
The power supply circuitry further controls gate voltages so that neither the gate to source, nor the gate to drain voltage for each of the pull up and pull down transistors exceeds the maximum tolerable voltage. Additionally, the power supply circuitry is itself configured so that voltage across the gate to source, gate to drain, or source to drain for each of its transistors does not exceed the maximum tolerable voltage.
The power supply circuitry further provides a tristate configuration so that voltages can be applied to the buffer output from an external source exceeding the maximum tolerable voltage without a voltage from the gate to source, gate to drain, or source to drain of a transistor in the output buffer exceeding the maximum tolerable voltage.